1. Technical Field
The embodiments described herein relate to a display device, and more particularly, to an output buffering circuit of a driver device, an amplifier circuit, and a display device employing the output buffering circuit.
2. Related Art
In general, demand for a low-power dissipation, high-speed, high resolution, and large output swing liquid crystal display (LCD) devices is increasing due to the development of compact, light-weight, low-power and high quality display devices. An LCD driver is commonly composed of source drivers, gate drivers, a controller, and a reference source. The source drivers play a particularly important role for achieving the demand, and include registers, data latches, digital-to-analog converters (DAC's) and output buffers. Here, the output buffers determine the speed, resolution, voltage swing and power dissipation of the source drivers. Due to a large number (typically several hundreds) of output buffers built into a single chip, the output buffer are required to occupy a small die area, and its power consumption is required to be sufficiently low.
FIG. 1 is a schematic diagram of a conventional source driver device. In FIG. 1, a conventional source driver device 100 includes an output buffering circuit 102 and a switching circuit 104.
The output buffering circuit 102 includes a first amplifier circuit 110 and a second amplifier circuit 120. The first amplifier circuit 110 receives a first input signal ‘SI1’ that is input from a D/A converter (not shown) and provides a first output signal ‘SO1’ to drive one source line on a display panel. Similarly, the second amplifier circuit 120 receives a second input signal ‘SI2’ that is input from the D/A converter and provides a second output signal ‘SO2’ to drive another source line on the display panel.
The first amplifier circuit 110 is coupled between an upper power supply VDDA and a lower power supply VSSA. Typically, the first amplifier circuit 110 includes an input stage (not shown), such as a differential pair, for receiving the first input signal ‘SI1’ and the first output signal ‘SO1’, and an output stage (not shown) for providing the first output signal ‘SO1’, wherein both of the input and output stages are coupled between the upper power supply VDDA and the lower power supply VSSA. Similarly, the second amplifier circuit 120 is coupled between the upper power supply VDDA and the lower power supply VSSA. The second amplifier circuit 120 typically includes an input stage (not shown), such as a differential pair, for receiving the second input signal ‘SI2’ and the second output signal ‘SO2’, and an output stage (not shown) for providing the second output signal ‘SO2’, wherein both of the input and output stages are coupled between the upper power supply VDDA and the lower power supply VSSA. Accordingly, the first and second amplifier circuits 110 and 120 both drive the display panel over an output driving range between VSSA and VDDA.
Assuming that icharge1=idischarge1 in long term where icharge and discharge denote the mean charging current and the mean discharging current, respectively, the mean power consumption P for the output stage in the first amplifier circuit 110 can then be expressed as:P=charge×(VDDA−VO1)+idischarge1×(VO1−VSSA)=icharge1×(VDDA−VSSA),where VO1 denotes the voltage of the first output signal ‘SO1’.
Assuming that icharge2=idischarge2 in long term where icharge2 and idischarge2 denote mean charge current and mean discharging current, respectively, the mean power consumption P for the output stage in the second amplifier circuit 120 can than be expressed as:P=charge2×(VDDA−VO2)+idischarge2×(VO2−VSSA)=icharge2×(VDDA−VSSA),where VO2 denotes the voltage of the second output signal ‘SO2’.
The switching circuit 104 includes a first switch SW1 and a second switch SW2 that are controlled by a control signal ‘SCTRL’. The first switch SW1 controls the coupling between the first amplifier circuit 110 and the source lines on the display panel. Similarly, the second switch SW2 controls the coupling between the second amplifier circuit 220 and the source lines on the display panel. By transitioning of the control signal ‘SCTRL’ between different levels, the first and second amplifier circuits 110 and 120 can take turns to drive different source lines on the display panel.
In general, design constraints considered when designing the source driver device 100 may include the ability of the source driver device 100 to drive large loads of the display panel, the dynamic and static power consumption of the source driver device 100, the complexity of design and manufacture of the source driver device 100, and/or other characteristics of the buffering circuit structure and operation. However, the source driver device 100 does not optimally satisfy all of the design constraints, particularly the power consumption.